Design for Test Intern

Apple Inc.

amount

Varies

awards available

Unspecified

deadline

Varies

Description

The Design for Test Intern is available to students enrolled in BSEE/MSEE, MSCE, or PhD program. You must have knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation, proven track record of high performance designs for low power applications, RTL design and timing closure on large complex designs, and SOC IP integration and RTL Design for performance, low area, and low power to be considered for this position. As an intern, you will be the heart of the chip design effort collaborating with all disciplines (vertical product model) with critical impact in getting functional products to millions of customers quickly.

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